SOI technology differs from traditional bulk semiconductor technologies in that the active semiconductor material of SOI technologies is typically much thinner than that utilized in bulk technologies. The active semiconductor material of SOI technologies will typically be formed as a thin film over an insulating material (typically oxide), with exemplary thicknesses of the semiconductor film being less than or equal to 2000 Å. In contrast, bulk semiconductor material will typically have a thickness of at least about 200 microns. The thin semiconductor of SOI technology can allow higher performance and lower power consumption to be achieved in integrated circuits than can be achieved with similar circuits utilizing bulk materials.
An exemplary integrated circuit device that can be formed utilizing SOI technologies is a so-called thin film transistor (TFT), with the term “thin film” referring to the thin semiconductor film of the SOI construction. In particular aspects, the semiconductor material of the SOI construction can be silicon, and in such aspects the TFTs can be fabricated using recrystallized amorphous silicon or polycrystalline silicon. The silicon can be supported by an electrically insulative material (such as silicon dioxide), which in turn is supported by an appropriate substrate. Exemplary substrate materials include glass, bulk silicon and metal-oxides (such as, for example, Al2O3). If the semiconductor material comprises silicon, the term SOI is occasionally utilized to refer to a silicon-on-insulator construction, rather than the more general concept of a semiconductor-on-insulator construction. However, it is to be understood that in the context of this disclosure the term SOI refers to semiconductor-on-insulator constructions. Accordingly, the semiconductor material of an SOI construction referred to in the context of this disclosure can comprise other semiconductive materials in addition to, or alternatively to, silicon; including, for example, germanium.
A problem associated with conventional TFT constructions is that grain boundaries and defects can limit carrier mobilities. Accordingly, carrier mobilities are frequently nearly an order of magnitude lower than they would be in bulk semiconductor devices. High voltage (and therefore high power consumption), and large areas are utilized for the TFTs, and the TFTs exhibit limited performance. TFTs thus have limited commercial application and currently are utilized primarily for large area electronics.
Various efforts have been made-to improve carrier mobility of TFTs. Some improvement is obtained for devices in which silicon is the semiconductor material by utilizing a thermal anneal for grain growth following silicon ion implantation and hydrogen passivation of grain boundaries (see, for example, Yamauchi, N. et al., “Drastically Improved Performance in Poly-Si TFTs with Channel Dimensions Comparable to Grain Size”, IEDM Tech. Digest, 1989, pp. 353-356). Improvements have also been made in devices in which a combination of silicon and germanium is the semiconductor material by optimizing the germanium and hydrogen content of silicon/germanium films (see, for example, King, T. J. et al, “A Low-Temperature (<=550° C.) Silicon-Germanium MOS TFT Technology for Large-Area Electronics”, IEDM Tech. Digest, 1991, pp. 567-570).
Investigations have shown that nucleation, direction of solidification, and grain growth of silicon crystals can be controlled selectively and preferentially by excimer laser annealing, as well as by lateral scanning continuous wave laser irradiation/anneal for recrystallization (see, for example, Kuriyama, H. et al., “High Mobility Poly-Si TFT by a New Excimer Laser Annealing Method for Large Area Electronics”, IEDM Tech. Digest, 1991, pp. 563-566; Jeon, J. H. et al., “A New Poly-Si TFT with Selectively Doped Channel Fabricated by Novel Excimer Laser Annealing”, IEDM Tech. Digest, 2000, pp. 213-216; Kim, C. H. et al., “A New High-Performance Poly-Si TFT by Simple Excimer Laser Annealing on Selectively Floating a Si Layer”, IEDM Tech. Digest, 2001, pp. 753-756; Hara, A. et al, “Selective Single-Crystalline-Silicon Growth at the Pre-Defined Active Regions of TFTs on a Glass by a Scanning CW Layer Irradiation”, IEDM Tech. Digest, 2000, pp. 209-212; and Hara, A. et al., “High Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallization”, IEDM Tech. Digest, 2001, pp. 747-750). Such techniques have allowed relatively defect-free large crystals to be grown, with resulting-TFTs shown to exhibit carrier mobility over 300 cm2N-second.
Another technique which has shown promise for improving carrier mobility is metal-induced lateral recrystallization (MILC), which can be utilized in conjunction with an appropriate high temperature anneal (see, for example, Jagar, S. et al., “Single Grain TFT with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization.”, IEDM Tech. Digest, 1999, p. 293-296; and Gu, J. et al., “High Performance Sub-100 nm Si TFT by Pattern-Controlled Crystallization of Thin Channel Layer and High Temperature Annealing”, DRC Conference Digest, 2002, pp. 49-50). A suitable post-recrystallization anneal for improving the film quality within silicon recrystallized by MILC is accomplished by exposing recrystallized material to a temperature of from about 850° C. to about 900° C. under an inert ambient (with a suitable ambient comprising, for example, N2). MILC can allow nearly single crystal silicon grains to be formed in predefined amorphous-silicon islands for device channel regions. Nickel-induced-lateral-recrystallization can allow device properties to approach those of single crystal silicon.
The carrier mobility of a transistor channel region can be significantly enhanced if the channel region is made of a semiconductor material having a strained crystalline lattice (such as, for example, a silicon/germanium material having a strained lattice, or a silicon material having a strained lattice) formed over a semiconductor material having a relaxed lattice (such as, for example, a silicon/germanium material having a relaxed crystalline lattice). (See, for example, Rim, K. et al., “Strained Si NMOSFETs for High Performance CMOS Technology”, VLSI Tech. Digest, 2001, p. 59-60; Cheng, Z. et al., “SiGe-On-Insulator (SGOI) Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation” 2001 IEEE SOI Conference Digest, October 2001, pp. 13-14; Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57-58; and Mizuno, T. et al., “High Performance CMOS Operation of Strained-SOI MOSFETs Using Thin Film SiGe-on-Insulator Substrate”, VLSI Tech. Digest, 2002, p. 106-107.)
The terms “relaxed crystalline lattice” and “strained crystalline lattice” are utilized to refer to crystalline lattices which are within a defined lattice configuration for the semiconductor material, or perturbed from the defined lattice configuration, respectively. In applications in which the relaxed lattice material comprises silicon/germanium having a germanium concentration of from 10% to 60%, mobility enhancements of 110% for electrons and 60-80% for holes can be accomplished by utilizing a strained lattice material in combination with the relaxed lattice material (see for example, Rim, K. et al., “Characteristics and Device Design of Sub-100 nm Strained SiN and PMOSFETs”, VLSI Tech. Digest, 2002, pp. 98-99; and Huang, L. J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, VLSI Tech. Digest, 2001, pp. 57-58).
Performance enhancements of standard field effect transistor devices are becoming limited with progressive lithographic scaling in conventional applications. Accordingly, strained-lattice-channeled-field effect transistors on relaxed silicon/germanium offers an opportunity to enhance device performance beyond that achieved through conventional lithographic scaling. IBM recently announced the world's fastest communications chip following the approach of utilizing a strained crystalline lattice over a relaxed crystalline lattice (see, for example, “IBM Builds World's Fastest Communications Microchip”, Reuters U.S. Company News, Feb. 25, 2002; and Markoff, J., “IBM Circuits are Now Faster and Reduce Use of Power”, The New York Times, Feb. 25, 2002).
Although various techniques have been developed for substantially controlling nucleation and grain growth processes of semiconductor materials, grain orientation control is lacking. Further, the post-anneal treatment utilized in conjunction with MILC can be unsuitable in applications in which a low thermal budget is desired. Among the advantages of the invention described below is that such can allow substantial control of crystal grain orientation within a semiconductor material, while lowering thermal budget requirements relative to conventional methods. Additionally, the quality of-the grown crystal formed from a semiconductor material can be improved relative to that of conventional methods.
In further aspects of the prior art, known dynamic random access memory (DRAM) devices include a switching transistor and an integrated storage capacitor tied to the storage node of the transistor. Incorporating a stacked capacitor or a trench capacitor in parallel with the depletion capacitance of the floating storage node enhances charge storage. Due to a finite charge leakage across the depletion layer, the capacitor is frequently recharged or refreshed to ensure-data integrity in the DRAM device. Thus, such a DRAM device is volatile. A power failure causes permanent data loss in a DRAM device. DRAM devices are relatively inexpensive, power efficient, and fast compared to non-volatile random access memory (NVRAM) devices.
A minimum capacitance per cell is required to sense a conventional DRAM cell. A significant challenge for every succeeding generation of reduced feature size is to provide this minimum capacitance per cell. A memory cell design goal is to achieve an 8F2 DRAM cell. To that end, complex three-dimensional capacitor structures have been designed. However, these complex three-dimensional capacitor structures are difficult to manufacture and adversely impact yield. There has been serious concern of the scalability of the conventional DRAM cell beyond the 0.1 μm lithographic generation. The scaling problems have been aggravated by increased device short channel effects and leakages associated with complicated capacitor structures. Thus, the elimination of the stacked capacitor or trench capacitor in a DRAM cell is desirable.
A silicon-on-insulator (SOI) capacitor-less single-transistor DRAM cell has been proposed by S. Okhonin et al. The state of the floating body charge in the transistor affects the channel conductance of the transistor and defines the memory state (“1” or “0”) of the cell. Two methods for generating-carriers in the body were proposed. The generated carriers are holes for the partially depleted (PD) SOI-NFET or electrons for the PD-SOI-PFET. One proposed method generates carriers using the drain-edge high field effect associated with impact ionization. In another case, the carriers are generated by the parasitic bipolar phenomenon.
The memory retention for these SOI capacitor-less single-transistor DRAM cells depends on the device channel length. That is, the stored charge retention time decreases with decreasing channel length. Additionally, the memory retention depends on charge recombination time constants and multiple recombination mechanisms, and thus is expected to be both temperature and process sensitive. Therefore, controlling the memory retention between refresh operations is expected to be difficult.
Known non-volatile random access memory (NVRAM), such as, Flash, EPROM, EEPROM, etc., store charge using a floating gate or a floating plate. Charge trapping centers and associated potential wells are created by forming nano-particles of metals or semiconductors in a large band gap insulating matrix, or by forming nano-layers of metal, semiconductor or a small band gap insulator that interface with one or more large band gap insulating layers. The floating plate or gate can be formed as an integral part of the gate insulator stack of the switching transistor.
Field emission across the surrounding insulator causes the stored charge to leak. The stored charge leakage from the floating plate or floating gate is negligible for non-volatile memory devices because of the high band gap insulator. For example, silicon dioxide (SiO2) has a 9 ev band gap, and oxide-nitride-oxide (ONO) and other insulators have a band gap in the range of 4.5 ev to 9 ev. Thus, the memory device retains stored data throughout a device's lifetime.
However, there are problems associated with NVRAM devices. The writing process, also referred to as “write-erase programming,” for non-volatile memory is slow and energy inefficient, and requires complex high voltage circuitry for generating and routing high voltage. Additionally, the write-erase programming for non-volatile memory involves high-field phenomena (hot carrier or field emission) that degrades the surrounding insulator. The degradation of the insulator eventually causes significant leakage of the stored charge. Thus, the high-field phenomena negatively affects the endurance (the number of write/erase cycles) of the NVRAM devices. The number of cycles of writing and erasing is typically limited to 1E6 cycles. Therefore, the available applications for these known NVRAM devices is limited.
Floating plate non-volatile memory devices have been designed that use a gate insulator stack with silicon-rich insulators. In these devices, injected charges (electrons or holes) are trapped and retained in local quantum wells provided by nano-particles of silicon embedded in a matrix of a high band gap insulator (also referred to as a “trapless” or “limited trap” insulator) such as silicon dioxide (SiO2) or silicon nitride (Si3N4). In addition to silicon trapping centers, other trapping centers include tungsten particles embedded in SiO2, gold particles embedded in SiO2, and a tungsten oxide layer embedded in SiO2.
It would be desired to provide dense and high speed capacitor-less memory cells with data non-volatility similar to Flash devices, and yet having DRAM-like endurance.